1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method of testing the same and, more particularly, to a semiconductor integrated circuit device having a high-speed serial data interface and a method of testing the same.
2. Description of the Related Art
A high-speed serial data interface has a serial data transmitter TX and serial data receiver RX.
To test the transmitter TX of this high-speed serial data interface, it is only necessary to output data at low speed and check the pattern of the output data.
In contrast, to test the receiver RX, data must be input to the receiver RX at high speed. Unfortunately, a test apparatus which outputs data at high speed, e.g., a so-called “high-speed tester” which outputs data at a “Gbit/s” class bit transfer rate or higher is very expensive. The cost required to install this expensive high-speed tester is directly reflected in the fabrication cost of semiconductor integrated circuit devices. To provide users with inexpensive semiconductor integrated circuit devices, the fabrication cost must be lowered by performing tests by more inexpensive methods.
As one inexpensive test method, loop-back testing by which output data from the transmitter TX is looped back to the receiver RX is known. A semiconductor integrated circuit device for which this loop-back testing can be performed is described in, e.g., reference 1 (see FIG. 1, and the section on loop-back testing on page 13).
In the known loop-back testing method, as shown in FIG. 15, output data from the transmitter TX is looped back to the receiver RX. This allows the receiver RX to be tested without using an expensive high-speed tester.
Reference 1: Texas Instruments, “TLK2501 1.5 TO 2.5 GBPS TRANSCEIVER”, [ONLINE] August 2000., [searched Aug. 25, 2003] Internet <hyperlink symbology omitted>
Unfortunately, the known loop-back testing method cannot raise the fault coverage of, in particular, a clock data recovery circuit (CDR).
The reason for this is as follows.
A CDR circuit includes a phase interpolator (PI). This PI is a circuit which, if offset (to be referred to as frequency offset hereinafter), is present between the frequency of a transmit data and the frequency of the clock in receiver, compensates a phase error produced by this frequency offset. If even a slight frequency offset is present, the PI activates itself and changes the phase of a clock to be generated. FIG. 16 shows the clock phase position diagram of a 16-phase clock switching type PI (clock 0→clock 1→clock 2→clock 3→clock 4→ . . . →clock 15). For example, when the phase is changed to clock 6, the phase is shifted by 3π/4 (135°). FIG. 17 shows an example in which a phase error present between the clock in transmitter and the clock in receiver is compensated by shifting the phase to clock 1.
In the known loop-back testing method, however, the clock source of the transmitter TX is the same as that of the receiver RX. Since the same clock source is used, there is no frequency offset between the clocks. The PI cannot properly activate itself if there is no frequency offset. For example, the PI keeps locking itself to a certain point in the clock phase position diagram. Accordingly, testing concerning this PI remains unsatisfactory, so the fault coverage of the CDR circuit does not rise.